1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a signal delay circuit.
2. Related Art
FIG. 1 is a block diagram of a conventional semiconductor integrated circuit, illustrating an example of signal transmission which is performed in a semiconductor integrated circuit.
Referring to FIG. 1, signals A and B are combined and processed by a signal combination unit 4. However, since the signals are transmitted through separate signal transmission paths, that is, signal A is transmitted through a signal transmission path 1 and the signal B is transmitted through a signal transmission path 2, the two signals may have different delay amounts. Therefore, the semiconductor integrated circuit may additionally include a signal delay circuit 3 such that the two signals meet each other within a sufficient timing margin. The signal delay circuit 3 controls a time margin between the two signals by adding a delay amount of the signal B which would otherwise arrive before signal A. Therefore, it is very important to constantly delay the signal B by the delay amount set by the signal delay circuit 3.
However, an external voltage VDD to drive the signal delay circuit 3 may be varied by various factors, and thus the delay amount may also be varied.
FIGS. 2A to 2C are waveform diagrams explaining the signal transmission of FIG. 1.
FIG. 2A is a waveform diagram when the external voltage VDD is at a normal level. The signals A and B are outputted as signals A_delay1 and B_delay1 through the signal transmission paths 1 and 2, respectively. In order to control the timing margin between the two signals, the signal B is additionally delayed into a signal B_delay2 through the signal delay circuit 3. Therefore, the signals A and B meet each other with a sufficient timing margin in the signal combination unit 4.
FIG. 2B is a waveform diagram when the external voltage VDD is at a low level. When the external voltage VDD for driving the signal delay circuit 3 is at a low level, the signal delay circuit 3 delays the signal B_delay1 by a longer time than the set delay amount, and outputs the delayed signal as the signal B_delay2, where signal B_delay2 is delayed longer than a proper amount and thus signal B_delay2 does not meet signal B_delay1 within a sufficient time margin in the signal combination unit 4.
FIG. 2C is a waveform diagram when the external voltage VDD is at a high level. When the external voltage VDD for driving the signal delay circuit 3 is at a high level, the signal delay circuit 3 delays the signal B_delay1 by a shorter time than the set delay amount, and outputs the delayed signal as the signal B_delay2, where signal B_delay2 is delayed shorter than a proper amount and thus B_delay2 does not meet signal B_delay1 within a sufficient time margin in the signal combination unit 4.
In the case of FIGS. 2B and 2C, the signals A and B meet each other with an insufficient margin. Therefore, a malfunction may occur in the entire semiconductor integrated circuit.